In recent years, the complexity of integrated circuits (ICs) has dramatically increased in both size and number of transistors, resulting in higher power consumption. A typical IC may have a wide range of power supply conditions, a number of independent voltage domains, and circuit performance objectives. Generally, different voltage domains are established depending upon performance needs for various functional blocks of an IC.
To reduce the power consumption, a typical IC includes multiple voltage domains, each domain being capable of operating in a different internal voltage level. In such an IC only the most performance critical portions of the design operate at a higher voltage. Hence, an IC having a first voltage domain powered by the VDD may have a second voltage domain operating at a certain fraction, for example 60%, of VDD. The first voltage domain may activate a first portion of the design, for example, 25% of the design, and the second portion of the design, covering for example 75%, of the design, may be activated by the second voltage domain. This simple design of two voltage domains significantly reduces the power consumption, because each portion of the design receives the power that it needs for its proper operation, rather than having the entire IC operating at VDD. The dynamic power consumption in digital circuits is proportional to the square of the operating voltage of the circuit. A person skilled in the art would note that the use of two power domains is merely an example, and that three or more power domains are possible too.
When an IC design includes multiple voltage domains, a level shifter is used to shift the voltage level of an output signal from a first voltage domain to the voltage level of a second voltage domain. A level shifter may transit the output signals from the lower level voltage to the higher level voltage and vice versa. A level shifter generally includes switching elements, such as transistors, that control the switching of the output signal between logical zero ‘0’ and logical one ‘1’ values.
Referring to FIG. 1 a schematic diagram of a typical prior art IC 100, including three voltage domains operating in different voltage levels, is shown. Voltage domain 110 operates at 0.7 volts (V), voltage domain 120 operates at 0.8V, and voltage domain 130 operates at 1V. An output signal 101 of voltage domain 110 is a 0.7V clock signal that is received at level shifters 140 and 150. Level shifter 140 shifts up the voltage level of signal 101 to a 0.8V of signal 102, and level shifter 150 shifts up the voltage level of signal 101 to a 1V signal 103. Signals 102 and 103 are now input signals of voltage domains 120 and 130 respectively. Output signal 104, having a 0.8V level of voltage domain 120, is shifted down by means of level shifter 160, to a 0.7V level of signal 106. Similarly, output signal 105 of voltage domain 130 is shifted down, by means of level shifter 170, from the 1V level of signal 105 to a 0.7V level of signal 107. Signals 106 and 107 are now input signals of voltage domain 110.
Process technologies now allow for creation of multiple voltage domains in IC designs. Even though the abstract idea of having voltage domains is a relatively simple one, there are significant challenges involved with the design of an IC that includes multiple voltage domains. One such challenge is to ensure a level conversion of the signals that cross voltage domain boundaries. When partitioning the design into multiple voltage domains, it is necessary to place appropriate level shifters for signals crossing unmatched voltage domains. That is, the designer has to identify all signals crossing unmatched voltage domains existing in the design. Each and every one of those signals has to be connected to an appropriate respective level shifter. In ICs where the number of voltage domains may be large, or where the number of signals crossing voltage domains is large, this is an inefficient, time-consuming, as well as error prone task. Furthermore, prior art design tools (e.g., computer aided design (CAD) tools), do not provide any automated means for checking the correctness of level shifters placed in the design. Moreover, such tools generally do not provide an automated method that inserts level shifters and appropriately places them in the IC design.